As known, the large-scale electronic circuitry system (e.g. a computer system) usually contains a plurality of subsystems. For achieving normal operations of these subsystems, a lot of power supply apparatuses are needed to provide various working voltage levels. Since the large-scale electronic circuitry system can provide various working voltage levels, a mixed-voltage input/output buffer circuit is employed to smoothly transmit signals.
FIG. 1 is a schematic circuit diagram illustrating a tri-state gate circuit used in the mixed-voltage input/output buffer circuit. As shown in FIG. 1, the tri-state gate circuit is a combination of a p-channel metal-oxide-semiconductor (PMOS) transistor 11 and an n-channel metal-oxide-semiconductor (NMOS) transistor 12. The source terminal 113 and the substrate 114 of the PMOS transistor 11 are both connected to a voltage source Vdd. The drain terminal 112 of the PMOS transistor 11 and the drain terminal 122 of the NMOS transistor 12 are both connected to a voltage output terminal Vout. The source terminal 123 and the substrate 124 of the NMOS transistor 12 are both connected to a ground terminal. The voltage output terminal Vout is connected to another circuit module (not shown). If the peak value of the working voltage of the circuit module is higher than the voltage level at the voltage source Vdd, some problems possibly occur.
Please refer to FIG. 1 again. The gate terminal 111 of the PMOS transistor 11 and the gate terminal 121 of the NMOS transistor 12 are served as signal input terminals. If the voltage applied to the gate terminal 111 of the PMOS transistor 11 is higher than the voltage level Vdd, the PMOS transistor 11 should be shut off without conduction. However, if the voltage level applied to the voltage output terminal Vout by the circuit module in the working status is higher than the voltage level Vdd, the parasitic diode 115 between the drain terminal 112 and the substrate 114 of the PMOS transistor 11 is forward biased. Whereas, if the voltage level applied to the voltage output terminal Vout is higher than the voltage level Vdd to a certain extent, a leakage current flowing from the drain terminal 112 to the voltage source Vdd through the parasitic diode 115 is possibly generated. The leakage current results in undesirable power consumption and device damage. Therefore, there is a need of providing an improved buffer circuit to obviate the drawbacks.